Hole trapping capability of silicon carbonitride charge trap layers★
Graduate School of Engineering, Tokai University, 4-1-1 Kitakaname, Hiratsuka, Kanagawa 259-1292, Japan
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Received in final form: 10 December 2019
Accepted: 2 June 2020
Published online: 14 July 2020
We have evaluated the hole trapping capability of the silicon carbonitride (SiCN) dielectric film for application in metal-oxide-nitride-oxide-silicon (MONOS)-type non-volatile memory devices. After a great number of holes were injected to the SiCN charge trap layer of memory capacitors at high applied voltages, the flat-band voltage shift ΔV fb,h of the capacitors was saturated and the charge centroid location of holes trapped in the SiCN layer was found to reach at 1.8–2.0 nm from the blocking oxide-charge trap layer interface. Using the obtained ΔV fb,h and charge centroid values, the maximum density of holes trapped in the SiCN layer was estimated to be 1.2 × 1013 holes/cm2, which was higher than that trapped in a silicon nitride charge trap layer (=1.0 × 1013 holes/cm2). It is concluded that the high density of trapped holes caused large ΔV fb,h in the memory capacitors with the SiCN layer.
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