https://doi.org/10.1051/epjap:2008109
Unified gate capacitance model of polysilicon thin-film transistors for circuit applications
Institute of Microelectronics, South China University of Technology, Guangzhou 510640, P.R. China
Corresponding author: dwanl@126.com
Received:
20
November
2007
Accepted:
15
May
2008
Published online:
24
June
2008
The characteristics of the gate capacitance at polysilicon thin-film transistors (poly-Si TFTs) based on terms of surface potential have been described and modeled in this paper. An explicit approximate relation for surface potential as a function of terminal voltages is developed. The theory is based on an assumed exponential distribution of trap states in the energy gap. Moreover, the model has been found to give an accurate description of the unique features of poly-Si TFTs, such as rapid increase of Cgs in leakage region and Cgd in kink region. The good agreement between simulated model results and experimental data confirms the accuracy and efficiency of this model.
PACS: 71.23.An – Theories and models; localized states / 73.40.Qv – Metal-insulator-semiconductor structures
© EDP Sciences, 2008
