https://doi.org/10.1051/epjap/2013120486
Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic*
1
Department of Information Processing, Tokyo Institute of Technology, Yokohama 226-8502, Japan
2
CREST, Japan Science and Technology Agency, Kawaguchi 332-0012, Japan
3
Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama 226-8502, Japan
a e-mail: syamamoto@ip.titech.ac.jp
Received:
22
October
2012
Accepted:
9
April
2013
Published online:
5
July
2013
We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks.
© EDP Sciences, 2013
