https://doi.org/10.1051/epjap:2001011
Impact of ultra-thinning on DC characteristics of MOSFET devices
Laboratory of Analysis and Architecture of Systems (LAAS) - CNRS, 7 avenue du Colonel Roche,
31077 Toulouse Cedex 4, France
Corresponding author: lepinois@laas.fr
Received:
18
December
2000
Revised:
16
May
2001
Accepted:
17
October
2001
Published online: 15 January 2002
The purpose of this paper is to highlight the impact of thinning on low and high levels DC characteristics of SmartMOS LDMOS devices. Both subthreshold and saturation current voltage deviations are discussed.
PACS: 85.30.De – Semiconductor-device characterization, design, and modeling / 85.30.Tv – Field effect devices
© EDP Sciences, 2002
